1. Field of the Invention
The present invention relates to a semiconductor memory device, more particularly to a semiconductor memory device capable of reducing or preventing data reading failure and a method for pre-charging the same.
2. Description of Related Art
Generally, a semiconductor device includes a first pre-charge circuit for pre-charging a pair of bit lines to a half power supply voltage, a second pre-charge circuit for pre-charging the first pre-charge circuit and a pair of data input/output lines to a half power supply voltage, and a third pre-charge circuit for pre-charging the pair of data input/output lines in a selected memory cell array block out of a plurality of memory cell array blocks during an active and a read operations to a power supply voltage.
In a conventional semiconductor memory device, pre-charge is performed such that a third pre-charge circuit pre-charges a pair of data input/output lines in a selected memory cell array block to a power supply voltage during a read operation, and a second pre-charge circuit pre-charges a pair of data input/output lines in a selected memory cell array to a half power supply voltage during a pre-charge operation.
FIG. 1 illustrates a schematic diagram of a semiconductor memory device in accordance with the conventional art. As shown in FIG. 1, the conventional semiconductor memory device includes a plurality of memory cell array blocks 10-1, . . . , 10-(k−1) and 10-k, a row decoder 12, a column decoder 14, a plurality of data input/output multiplexers 16-11, . . . , 16-kk, a plurality of data input/output sense amplifiers 18-11 to 18-kk, a power supply voltage IVC generating circuit 20, a pre-charge voltage VBL generating circuit 22. The semiconductor memory device further includes bit line pre-charge circuits BLPRE1 connected to bit line pairs (ABL1, ABL1B), (ABL2, ABL2B), . . . , respectively, arranged on a left side of the memory cell array blocks 10-1 to 10-k, and bit line pre-charge circuits BLPRE2 connected to bit line pairs (ABL1, ABL1B), (ABL2, ABL2B), . . . , respectively, arranged on a right side of the memory cell array blocks 10-1 to 10-k. The semiconductor memory device also further includes sense amplifiers BLSA 24 connected to sense bit line pairs (SBL1, SBL1B), (SLB2, SBL2B), . . . , respectively, in the respective memory cell array blocks 10-1 to 10-k, data input/output gates (DIOG), bit line isolating gates ISOG1 connected between the respective sense bit line pairs (SBL1, SBL1B), (SLB2, SBL2B), . . . , and the respective array bit line pairs (ABL1, ABL1B), (ABL2, ABL2B), . . . , arranged on the left side of the memory cell array blocks 10-1 to 10-k, bit line isolating gates ISOG2 connected between the respective sense bit line pairs (SBL1, SBL1B), (SLB2, SBL2B), . . . and the respective array bit line pairs (ABL1, ABL1B), (ABL2, ABL2B), . . . arranged on the right side of the memory cell array blocks 10-1 to 10-k, pre-charge circuits IVCPRE11 . . . and IVCPREkk connected to the respective data input/output lines (IO11, IO11B), . . . and (IOkk, IOkkB), pre-charge circuits VBLPRE11, . . . , and VBLPREkk, data input/output multiplexers (IOMUX) 16-11, . . . , and 16-kk and data input/output sense amplifiers (IOSA) 18-11, . . . , and 18-kk.
In FIG. 1, the data input/output line pairs (IO11, IO11B)-(IOkk, IOkkB) are signal lines common to adjacent memory cell array blocks 10-n, 10-(n+1). Further, circuits connected to the data input/output line pairs (IO11, IO11B)-(IOkk, IOkkB) are common to the adjacent memory cell array blocks 10-n, 10-(n+1). Further, circuits connected to the sense bit line pairs (SBL1, SBL1B), (SBL2, SBL2B), . . . are common to the adjacent memory cell array blocks 10-n, 10-(n+1).
Each of the data input/output gates DIOG comprises NMOS transistors N1 and N2. Each of the bit line isolating gates ISOG1, ISOG2 comprises NMOS transistors N3 and N4. Each of the bit line pre-charge circuits BLPRE1, BLPRE2 comprises of NMOS transistors N5, N6 and N7. Each of the pre-charge circuits IVCPRE11-IVCPREkk comprises NMOS transistors N8, N9 and N10. Each of the pre-charge circuits VBLPRE11-VBLPREkk comprises NMOS transistors N11, N12 and N13.
Functions of each block shown in FIG. 1 will be described below.
The row decoder 12 decodes a row address RA and generates word line section signals WL1-WLm. The column decoder 14 decodes a column address CA and generates column selection signals CSL1-CSLn. The respective data input/output gates DIOG are turned on in response to the respective column selection signals CSL1-CSLn and transfer data between the respective sense bit line pairs (SBL1, SBL1B), (SBL2, SBL2B) and the respective data input/output line pairs (IO11, IO11B)-(IOkk, IOkkB). The bit line sense amplifier 24 amplifies voltage difference between each sense bit line pair (SBL1, SBL1B), (SBL2, SBL2B), . . . The bit line isolation gates ISOG1, ISOG2 are turned on in response to bit isolation control signals ISO1, ISO2, . . . , of a power supply voltage level during a pre-charge operation, and completely turned on in response to the bit line isolation control signals ISO1, ISO2, . . . , of a high voltage level during an active operation. Each of the pre-charge circuits BLPRE1, BLPRE2 pre-charges the array bit line pairs (ABL1, ABL1B), (ABL2, ABL2B), . . . and the sense bit line pairs (SBL1, SBL1B), (SBL2, SBL2B), . . . to a voltage VBL level in response to the pre-charge control signals PRE1, PRE2, . . .
A value of the voltage VBL is a half power supply voltage value. Each of the pre-charge control signals PRE1, PRE2, . . . is transitioned from logic “low” level to logic “high” level in response to a corresponding block selection signal which is used for selecting the respective memory cell array blocks 10-1 to 10-k. Each of the pre-charge circuits IVCPRE11-IVCPREkk charges the respective data input/output line pairs (IO11, IO11B)-(IOkk, IOkkB) to a power supply voltage IVC in response to respective pre-charge control signals A11-Akk. Each of the pre-charge circuits VBLPRE11-VBLPREkk pre-charges the data input/output pairs (IO11, IO11B)-(IOkk, IOkkB) to the voltage VBL in response to respective pre-charge control signals B11-Bkk. Each of the data input/output multiplexers 16-11 to 16-kk transmits respective output signals of the data input/output sense amplifiers 18-11 to 18-kk to the respective data input/output line pairs (IO11, IO11B)-(IOkk, IOkkB) in response to the block selection signal during a write operation, and transmits respective signals of the data input/output line pairs (IO11, IO11B)-(IOkk, IOkkB) to the respective data input/output sense amplifiers 18-11 to 18-kk in response to a block selection signal during a read operation. The data input/output sense amplifiers 18-11 to 18-kk amplify current differences between respective output signals output from the data input/output multiplexers 16-11 to 16-kk and then output the amplified signals.
A read operation of the semiconductor memory device shown in FIG. 1 is described below, wherein a memory cell array block 10-1 of the memory cell array blocks 10-1 to 10-k is selected for data reading.
When the array bit line pairs (ABL1, ABL1B), (ABL2, ABL2B), . . . and the sense bit line pairs (SBL1, SBL1B), (SBL2, SBL2B) . . . are pre-charged, and an active command is applied along with the row address RA and a block address (not shown), the row decoder 12 decodes the row address RA and generates a word line selection signal WL1 for selecting a word line in the memory cell array 10-1. If a block selection signal for selecting the memory cell array block 10-1 is generated in response to a block address, the bit line pre-charge control signal PRE1 transitions from logic “high” level to logic “low” level, and the bit line isolation control signal ISO1 transitions from logic “low” level to logic “high” level in response to the block selection signal. Then, the pre-charge circuits PRE1, PRE2 are turned off, and the bit line isolation gates ISOG1, ISOG2 are completely turned on, so that a charge sharing operation occurs between the memory cells connected to a word line activated in response to the word line selection signal WL1 and the array bit line pairs (ABL1, ABL1B), (ABL2, ABL2B). As a result, a voltage difference is generated between the sense bit line pairs (SBL1, SBL1B), (SBL2, SBL2B), and the bit line sense amplifier BLSA 24 operates to amplify the voltage difference. At this time, the control signals A11, A12 transitions to logic “high” level and the control signals B11, B12 transitions to logic “low” level. Then, the multiplexers 16-11 and 16-12 are turned on. Accordingly, the data input/output line pairs (IO11, IO11B), (IO12, IO12B) transitions to a power supply voltage IVC level.
If the read command and the column address are applied together, the column decoder 14 decodes a column address CA and generates a column selection signal CSL1. The data input/output gates DIOG are turned on in response to the column selection signal CSL1 to transmit the amplified signal of the sense bit line pairs (SBL1, SBL1B), (SBL2, SBL2B) to the data input/output line pairs (IO11, IO11B), (IO12, IO12B). The data transmitted to the data input/output line pairs (IO11, IO11B), (IO12, IO12B) are output through the data input/output multiplexers 16-11, 16-12. The data input/output sense amplifiers 18-11, 18-12 amplify current differences between signals output from the data input/output multiplexers 16-11, 16-12. That is, when the data input/output line pairs (IO11, IO11B), (IO12, IO12B) are pre-charged to the power supply voltage IVC level and the data input/output gates (IO11, IO11B), (IO12, IO12B) are turned on, the data input/output line (or complementary data input/output line) connected to the sense bit line (or complementary sense bit line) of logic “high” level maintains the power supply voltage IVC level, but the complementary data input/output line (or the data input/output line) connected to the complementary sense bit line (or the sense bit line) of logic “low” level loses voltage. Accordingly, current does not flow between the sense bit line (or complementary sense bit line) and the data input/output line (or complementary data input/output line) but flows between the complementary sense bit line (or sense bit line) and the complementary data input/output line (or data input/output line). At this time, the data input/output sense amplifiers 18-11, 18-12 amplify current differences between the data input/output line pairs (IO11, IO11B), (IO12, IO12B) and output the amplified signal.
After the read operation is performed, a pre-charge command is applied. At this time, the pre-charge control signal PRE1 and control signals B11, B12 transition to logic “high” level, and control signals A11, A12 transition to logic “low” level. Accordingly, the array bit line pairs (ABL1, ABL1B), (ABL2, ABL2B) and the sense bit line pairs (SBL1, SBL1B), (SBL2, SLB2) are pre-charged to the voltage VBL1 level, and the data input/output line pairs (IO11, IO11B), (IO12, IO12B) are pre-charged to the voltage VBL level from the power supply voltage IVC level. Thus, charges on the data input/output line pairs (IO11, IO11B), (IO12, IO12B) are drawn to the voltage VBL line through the NMOS transistors N12, N13 forming the pre-charge circuits VBLPRE11, VBLPRE12. At this time, the data input/output line pairs (IO11, IO11B), (IO12, IO12B) may not be discharged completely because the voltage VBL generating circuit has low driving capability, so that voltage level of the voltage VBL line increases.
Accordingly, the pre-charge level of the array bit line pairs (ABL1, ABL1B), (ABL2, ABL2B), . . . in the memory cell array blocks 10-1 to 10-k, the sense bit line pairs (SBL1, SBL1B), (SBL2, SBL2B), . . . , and the data input/output line pairs (IO11, IO11B)-(IOkk, IOkkB) increases.
As a result, when charge sharing occurs between the selected memory cells and the bit line pair, the voltage difference decreases, so that it causes a problem that the bit line sense amplifiers may not correctly amplify signals of the bit line pairs.
FIG. 2 illustrates a conventional voltage VBL generating circuit 22 including PMOS transistors P1, P2 and P3, and NMOS transistors N14, N15 and N16.
Operation of the voltage VBL generating circuit in FIG. 2 is described below.
If a voltage level of a node A is a half power supply voltage ½ IVC, a voltage level of a node C becomes (½ IVC+VTN) and a voltage level of a node D becomes (½ IVC−VTP), where VTN and VTP are threshold voltages of the NMOS and PMOS transistors N14 and P2, respectively. The NMOS transistor 14 and the PMOS transistor P2 are almost turned on, i.e. not completely turned on, and a stable ½ IVC level is generated and transmitted to the voltage VBL generating line.
In this situation, if the output voltage VOUT level is lowered, resistance of the PMOS transistor P1 decreases and resistance of the NMOS transistor N15 increases, so that the voltage of the node A increases. Then, the voltage of the node C increases but the voltage of the node D decreases, so that the NMOS transistor N16 is turned on and the PMOS transistor P3 is turned off. As a result, the voltage of the node B increases.
On the other hand, if the output voltage VOUT increases, resistance of the PMOS transistor P1 increases and resistance of the NMOS transistor N15 decreases, so that the voltage of the node A decreases. Then, the voltage of the node C decreases but the voltage of the node D increases, so that the NMOS transistor N16 is turned off and the PMOS transistor P3 is turned on. As a result, the voltage of the node B decreases.
As described above, the voltage VBL generating circuit 22 generates a signal with stable voltage VBL level.
The voltage VBL generating circuit in FIG. 2 may have a high driving capability when magnitude of variation of the voltage VBL level is great.
Accordingly, only increasing a size of transistors in the voltage VBL generating circuit may not help lower a voltage level of the voltage VBL generating line and smoothly discharge the charges on the voltage VBL generating line, the charges being drawn from the data input/output line pairs in a selected memory cell array block when operation of the semiconductor memory device changes from the read operation to the pre-charge operation.
That is, increasing the size of the transistors in the voltage VBL generating circuit is not a good solution to lower the voltage level of the voltage VBL generating line, because this solution increases current consumption and layout area of the voltage VBL generating circuit.
An industry trend is that an integration degree of semiconductor memory devices increases and operating voltage decreased. However, as the integration degree increases and the operating voltage decrease, current driving capability of transistors in the semiconductor memory device decreases, and it has become more difficult to pre-charge the data input/output lines to a stable half power supply voltage level during the pre-charge operation. That is, during a normal pre-charge operation following the read operation, the second pre-charge circuit discharges data input/output lines so that charges on the data input/output lines are drawn to a half power supply voltage generating circuit. However, because the driving capability of the transistor is low, the data input/output lines are not sufficiently discharged. As a result, the pre-charge voltage level of the data input/output lines increases when each the pre-charge operation is performed.